1. Field of the Invention
The present invention relates to compressive receivers, and more particularly relates to a circuit and method for improving the sensitivity to continuous wave (CW) signals presented to a compressive receiver.
2. Description of the Prior Art
Compressive receivers are well known in the prior art. Referring to FIG. 1, the architecture of a traditional compressive receiver (CR) 2 is illustrated in block diagram form. In a CR, a radio frequency (RF) amplifier 4 receives and amplifies a broad band radio signal. Following the RF amplifier 4 is a mixer 6. An output terminal of the RF amplifier 4 is operatively coupled to an RF input port 6A of the mixer 6 which receives the amplifier signal.
The CR also includes a swept local oscillator (SLO) 8 which has an associated output port 8A. The SLO 8 generates a frequency sweep which is linearly changing with time from a first frequency (F1) to a final frequency (F2), over a fixed time period known as the compressive receiver sweep time (.tau..sub.s). The SLO is characterized by a slope which is equal to ##EQU1## The bandwidth of the compressive receiver is equal to the difference in frequencies, F2-F1, and is typically several hundred megahertz wide. The SLO output port 8A is coupled to a local oscillator (LO) input port 6B of the mixer 6.
The mixer 6 further includes an intermediate frequency (IF) output port 6C. The mixer 6 generates an output signal corresponding to the sum and the difference of the signals presented to the RF input port 6A and the LO input port 6B. This mixer output signal is presented on the IF output port 6C.
The compressive receiver further includes a dispersive delay line (DDL) 10 which has both an input terminal and an output terminal. The input terminal of the DDL 10 is operatively coupled to the IF output port 6C and receives the mixer output signal. The DDL 10 exhibits a linear variable frequency delay over the CR bandwidth and generates a time domain output signal which is representative of the frequency domain signal presented to the DDL 10 input terminal. The slope of the linear variable delay of the DDL 10 is equal and opposite to the slope of the SLO 8. Therefore, the slope of DDL 10 can be stated as: ##EQU2## As a result of the related slopes of SLO 8 and the DDL 10, the output signal from the DDL 10 is a compressed frequency domain output voltage which corresponds to the radio signal presented to the input terminal 4A of RF amplifier 4.
Following the DDL 10, the compressive receiver includes a detector 11. The detector 11 receives the compressed frequency domain signal and generates a corresponding compressed time domain voltage signal. A conventional detector 11 is formed using a successive detection log amp. The output signal from the detector 11 is the compressive receiver video output signal.
The compressive receiver further includes a center of pulse (COP) detector 12 which has both an input terminal and an output terminal. The input terminal of the COP detector 12 is operatively coupled to the output detector 11 and receives the CR video output signal. The COP detector 12 determines when carrier signals are present in the compressive receiver video output signal and generates a strobe signal corresponding to these carrier signals. Following the COP detector 12 is a frequency/amplitude encoder 14 which has both input and output terminals. The input terminal of the frequency/amplitude encoder 14 is operatively coupled to the output terminal of the COP detector 12. The frequency/amplitude encoder 14 receives the strobe signals from the COP detector 12 and measures the relative time of the strobe signals to determine the actual frequency of the carrier signals. The frequency/amplitude encoder 14 also evaluates the magnitude of the CR video output signal and calculates the equivalent RF power of this signal. The frequency/amplitude encoder 14 creates a digital signal corresponding to the frequency and amplitude of received carrier signals and presents this digital signal on its output terminal.
The CR also includes a signal track and control circuit 16. The signal track and control circuit 16 includes an input terminal which is operatively coupled to the output terminal of the frequency/amplitude encoder 14. The signal track and control circuit 16 receives the frequency and amplitude data from the frequency/amplitude encoder 14 for each sweep of the CR bandwidth and averages this data. The signal track and control circuit 16 also measures the pulse width and time of arrival of the CR video output signal to determine an end of pulse condition. The signal track and control circuit 16 further includes an output terminal which is operatively coupled to a pulse formatter 18. Once the end of pulse condition has been determined, the signal track and control circuit 16 forwards the frequency, amplitude, pulse width and time of arrival data to the pulse formatter 18.
The pulse formatter 18 further includes a pulse descriptor word (PDW) output port 18a. The pulse formatter 18 formats the data signals from the signal track and control circuit 16 and generates a pulse descriptor word output signal which is presented on the PDW output port 18a.
While such a compressive receiver topology features a significantly higher sensitivity for the given bandwidth as compared to traditional receiving systems, there is still a need to further improve the small signal detection performance of CW signals presented to the input of compressive receiver systems.